The increasing tightness of the chip structures leads to more and more increasing noise problems while determining the state of a Symmetrical Random Access Memory Cell (SRAM) according to the state of the art or while writing said cell. Furthermore negative side effects on neighboring cells occur.
Known solutions are cells with larger devices or more devices, especially 8T (eight transistor) cell approaches. But because of the needed massive usage of cells the area of a cell is essential. So such approaches have an inevitable drawback.
The prior art Jean-Marc Masgonty, Stefan Cserveny, Christian Piguet, “Low-Power SRAM and ROM Memories”, PATMOS 2001, Yverdon-les-bains, Switzerland, Sep. 26-28, 2001, p 7.4.1-7.4.8, describes a memory cell operation of a common 6T SRAM wherein it is proposed to write it in a conventional way while using the true and inverted bit-lines, but to read only through a single bit-line to overcome noise problems on a memory design where no sense amplifiers are present. For evaluation of the stored state an circuitry controlling the complex use of the bit-lines is necessary.
The prior art Navid Azizi, Farid N. Najm, Andreas Moshovos, “Low-Leakage Asymmetric-Cell SRAM”, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 4, AUGUST 2003, p. 701-715 describes asymmetric SRAM cells that reduce leakage power in caches while maintaining low access latency. A major drawback on this technique is the need of novel sense amplifier in combination with dummy bit-lines, that would be needed to allow read times to be on par with conventional symmetric cells.